Method and device to increase latch-up immunity in cmos device

ABSTRACT

The preferred embodiment of the present invention overcomes the imitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by reducing the mobility of carriers between the devices. The preferred embodiment uses an implant formed beneath trench isolation between n-channel and p-channel devices. This implant preferably comprises relatively large/heavy elements implanted into the wafer beneath the trench isolation. The implant elements reduce the mobility of the charge carriers. This increases the latch-up holding voltage and thus reduces the likelihood of latch-up. The implants can be formed without the need for additional photolithography masks.

BACKGROUND OF THE INVENTION

[0001] 1. Technical Field

[0002] This invention generally relates to semiconductor devices, andmore specifically relates to methods and structures to increase latch-upimmunity.

[0003] 2. Background Art

[0004] As integrated semiconductor devices continue to grow incomplexity, there is a constant need to increase the density of thesemiconductor devices. This increase in density creates several problemsthat can cause device failures if not addressed. One such problem is thepropensity for semiconductor devices, particularly CMOS devices, to“latch-up.” Latch-up is a well known problem caused by unwantedtransistor action between elements of the integrated circuit. Thisunwanted transistor action can be triggered by a wide variety of events,and can cause the semiconductor device to fail.

[0005] Latch-up is generally caused by the close proximity of n-channeland p-channel devices in modern CMOS devices. For example, a typicalCMOS device fabricated on a p-type substrate would contain a p-channeldevice fabricated in a n-well (or n-type region) and an n-channel devicefabricated in a p-well (or p-type region), with only a short distancebetween the wells. This structure inherently forms a parasitic lateralbipolar structure (npn) and parasitic vertical bipolar structure (pnp).Under certain biasing conditions the pnp structure can supply basecurrent to npn structure (or vice versa), causing a large current toflow from one well to the other well. This large current can damage theCMOS device.

[0006] The propensity for CMOS devices to latch-up has been addressed inseveral ways. One way involves reducing the “gain” or beta of thetransistor (npn and pnp). This generally reduces the propensity of theCMOS device to latch-up by increasing the trigger voltage/current, wherethe trigger voltage/current is the voltage/current that must be appliedto a node to induce latch-up.

[0007] Another method in dealing with latch-up is to raise the latch-upholding voltage. The latch-up holding voltage is the lowest stablevoltage that can support a large current after latch-up is triggered. Byincreasing the latch-up holding voltage, the latch-up immunity isincreased and the likelihood of the circuit being damaged is decreased.The optimal situation is to have a holding voltage greater than theburn-in voltage, typically 1.5 volts above the nominal supply voltage(Vdd).

[0008] Shallow trench isolation (STI) has been used between then-channel and p-channel devices to minimize the likelihood of latch-up.However, as device density continues to increase the STI depth tends todecrease. This causes the latch-up holding voltage to be reduced. If thelatch-up holding voltage is reduced significantly, i.e., to less thanthe bum-in voltage, the reliability of the device can be negativelyimpacted.

[0009] Thus, there is a need for improved methods for increasing thelatch-up immunity of CMOS devices by increasing the latch-up holdingvoltage.

DISCLOSURE OF INVENTION

[0010] The present invention overcomes the limitations of the prior artand provides a device and method to increase the latch-up immunity ofCMOS devices by reducing the mobility of charge carriers between thedevices. The preferred embodiment uses an implant formed beneath trenchisolation between n-channel and p-channel devices. The implant reducesthe mobility of the carriers wich flow from P+ regions to N+ regions andvice versa. This increases the latch-up holding voltage and thusimproves the reliability of the technology. The implants can be formedwithout the need for additional photolithography masks. The advantage ofthe present invention is to increase the immunity to latch-up withoutadding undue complexity to the manufacturing process or requiring alarger area on the semiconductor substrate.

[0011] The foregoing and other advantages and features of the inventionwill be apparent from the following more particular description of apreferred embodiment of the invention, as illustrated in theaccompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0012] The preferred exemplary embodiment of the present invention willhereinafter be described in conjunction with the appended drawings,where like designations denote like elements, and

[0013]FIG. 1 is a cross sectional side view of a wafer portion;

[0014]FIG. 2 is a cross sectional side view of a wafer portion withafter trench etch for shallow trench isolation;

[0015]FIG. 3 is a cross sectional side view of a wafer portion with ashallow trench isolation with sidewall oxidation;

[0016]FIG. 4 is a cross sectional side view of a wafer portion with ashallow trench isolation and an implant beneath the shallow trenchisolation;

[0017]FIG. 5 is a cross sectional side view of a wafer portion with afinished shallow trench isolation and an implant beneath the shallowtrench isolation; and

[0018]FIG. 6 is a cross sectional side view of a wafer portion withdevices fabricated in the n-well and p-well.

BEST MODE FOR CARRYING OUT THE INVENTION

[0019] The preferred embodiment of the present invention overcomes thelimitations of the prior art and provides a device and method toincrease the latch-up immunity of CMOS devices by decreasing carriermobility between n-channel and p-channel devices. This is accomplishedby forming an implant between the devices. In the preferred embodiment,the implant is formed beneath a shallow trench isolation (STI) betweenthe n-channel and p-channel devices. The implant can be formed withoutrequiring additional high energy implants or additional mask levels.

[0020]FIG. 1 is a cross-sectional schematic view of wafer portion 100 onwhich a CMOS device will be fabricated. In the preferred embodiment, thewafer portion 100 comprises a p+ substrate with a p− epitaxial layer atthe top portion. Of course other suitable substrate materials can beused.

[0021] Turning to FIG. 2, according to the preferred embodiment, shallowtrench isolation (STI) 102 is used to separate n-channel from p-channeldevices. The STI can be formed with any suitable processing method, suchas reactive ion etching (RIE). For example, a masking layer 104 isdeposited across the wafer 100. The masking layer can comprise anysuitable material, for example, a layer of silicon dioxide (SiO₂) undera layer of silicon nitride (SiN) is a commonly used material that may bepatterned to form an etch mask. The masking layer 104 is then patternedusing conventional photolithography techniques. The STI 102 is thenformed by etching away portions of the wafer no longer covered bymasking layer 104.

[0022] This forms the shallow trench isolation 102. Further processingsteps will form n-channel devices and p-channel devices on the waferportion 100. Isolation regions such as STI 102 are formed between thesevarious devices (i.e., between two n-channel devices, between twop-channel devices and between an n-channel and a p-channel device. Inall these cases the STI 102 serves to isolate the devices from eachother.

[0023] As will become clear, the preferred embodiment results in lessmobility for carriers beneath the STI 102 and thus allows the STI 102 tobe more shallow than prior art STI's and still maintain effectiveisolation between devices. Thus, the preferred embodiment improves thescalibility of STI without decreasing the latch-up immunity.

[0024] Turning now to FIG. 3, the next step is to grow sidewalloxidation 110 (suitably SiO₂) in the STI trench. The sidewall oxidation110 serves to reduce stress incurred by the STI etch and to removesurface contaminants.

[0025] According to the preferred embodiment, the latch-up immunity isincreased by reducing the mobility of carriers that travel under the STI102. In particular, an implant or implants are used that improves thelatch-up holding voltage. These implants can be made without additionalmasks.

[0026] Turning to FIG. 4, a species is implanted forming implant 106underneath STI 102. The implantation can be done with any suitableprocedure, such as traditional ion implantation techniques. The maskinglayer 104 blocks the implants from entering the other portions of wafer100. Thus, the implant is self aligned, and does not require additionalmasks or process steps.

[0027] The implants can comprise any suitable material that wouldsufficiently degrade conductor mobility beneath STI 102. Preferablyelements for implants are selected to minimize n-well or p-wellcounterdoping, and as such the preferred implant would result in minimaldoping change for the adjacent n-wells or p-wells. Additionally, thepreferred implant should be selected to have low diffusitivity, thusreducing the probability of the implants diffusing into neighboringdevices.

[0028] Thus, the elements preferably comprise large, heavy elements.Large elements result in an increased probability of scattering, andhence significantly decrease the mobility of the conductors beneath theSTI. When latch-up occurs, the current flows almost entirely beneath theSTI 102, thus reductions in the mobility beneath the STI 102 willincrease the latch-up holding voltage.

[0029] The preferred implants can be electrically neutral species, suchas argon (Ar), germanium (Ge), oxygen (O), nitrogen (N), and would thusdecrease the mobility of carriers with a very low change to the dopantprofile of the substrate. In the alternative, the implants can be p-typeand n-type materials used in combination to reduce the mobility whileresulting a low net dopant profile changes. In these cases species suchas indium (In) in combination with antimony (Sb) and phosphorus (P) incombination with boron (B) can be used. These elements, when implantedunder the STI 102 causes the mobility of the carriers beneath the STI102 to decrease. This increases the latch-up holding voltage andincreases latch-up immunity.

[0030] Thus, the implants are preferably either a counter dopingcombination of n-type and p-type materials to minimize effects toneighboring wells, or an electrically inactive species. The implants arepreferably implanted at relatively low energies to keep the implantsdirectly under the STI 102.

[0031] In an alterative embodiment, the implant 106 is formed before theformation of the sidewall oxidation 110.

[0032] Turning now to FIG. 5, the fabrication of the wafer continues. Inparticular, the STI trench is then filled and the wafer 100 is thenplanaraized with a chemical mechanical polish (CMP). This removes theremaining masking layer 104 and excess sidewall oxidation, resulting inthe finished shallow trench isolation.

[0033] The individual devices are now fabricated on both sides of theshallow trench isolation. Turning to FIG. 6, an example of completeddevices are shown. In particular, a n-channel device, including a gate602, gate oxide 604 and diffusions 606 and 608 are formed in the p-well610. Likewise, a p-channel device including a gate 612, gate oxide 614and diffusions 616 and 618 are formed in the n-well 620. In accordancewith the preferred embodiment, the implant 106 serves to increase thelatch-up holding voltage by reducing carrier mobility between thedevices. This increases the latch-up immunity of the CMOS devices.

[0034] While the invention has been particularly shown and describedwith reference to a preferred exemplary embodiment with an CMOS deviceusing shallow trench isolation, it will be understood by those skilledin the art that various changes in form and details may be made thereinwithout departing from the spirit and scope of the invention. Inparticular any type of implant can be made that would reduce themobility of the carriers beneath the STI.

1. An isolation structure for increasing the latch-up holding voltage in a CMOS device fabricated in a semiconductor substrate, the isolation structure comprising: a) a shallow trench fabricated in said semiconductor substrate; and b) an implant, said implant formed below said trench in said semiconductor substrate, said implant reducing the mobility of carriers in said substrate beneath said shallow trench.
 2. The isolation structure of claim 1 wherein said implant comprises n-type and p-type species and results in low net dopant profile change.
 3. The isolation structure of claim 1 wherein said implant comprises an electrically neutral species.
 4. The isolation structure of claim 1 wherein said implant comprises argon.
 5. The isolation structure of claim 1 wherein said implant comprises oxygen.
 6. The isolation structure of claim 1 wherein said implant comprises germanium.
 7. The isolation structure of claim 1 wherein said implant comprises nitrogen.
 8. The isolation structure of claim 1 wherein said implant comprises indium and antimony.
 9. The isolation structure of claim 8 wherein said indium and antimony implant comprises a nearly electrically neutral combination.
 10. The isolation structure of claim 1 wherein said implant comprises boron and phosphorus.
 11. The isolation structure of claim 10 wherein said boron and phosphorus comprises a nearly electrically neutral combination.
 12. A method for reducing the damaging effects of latch-up in CMOS devices comprising the steps of: a) providing a semiconductor substrate; b) defining a shallow trench in said semiconductor substrate; and c) implanting a mobility degrading species below said shallow trench.
 13. The method of claim 12 wherein said mobility degrading species comprises n-type and p-type species in combination to provide low net dopant profile change.
 14. The method of claim 12 wherein said mobility degrading species comprises a neutral species to provide low dopant profile change.
 15. The method of claim 12 wherein said mobility degrading species comprises argon.
 16. The method of claim 12 wherein said mobility degrading species comprises oxygen.
 17. The method of claim 12 wherein said mobility degrading species comprises germanium.
 18. The method of claim 12 wherein said mobility degrading species comprises nitrogen.
 19. The method of claim 12 wherein said mobility degrading species comprises indium and antimony.
 20. The method of claim 12 wherein said mobility degrading species comprises boron and phosphorus. 